Electro-static discharge protection circuits (hereinafter “ESD circuits”) are provided on many semiconductor integrated circuits (hereinafter “chips”) to help prevent sudden failure due to discharge of static electricity through the chip by way of the chip's external terminals. Such failures, while once common, are much less common now that ESD circuits are widely used.
ESD circuits occupy fairly large areas of a chip in order to be ready to sink the large amount of current that can occur during an electro-static discharge. Static charges can have voltages measuring in the thousands of volts. Currents more than 100 times higher and sometimes more than 1000 times higher than that present during normal operation have been known to flow through a single external terminal of a packaged chip. If currents in such ranges are to be handled while preventing the chip from being permanently damaged, the current has to be spread out to devices, conductors, and/or the substrate, etc., in a manner such that no single such device or conductor conducts more current than it can safely handle. Otherwise, the consequences can be catastrophic: conductors can melt, reflow, and/or vaporize, and semiconductor materials can melt and/or recrystallize.
However, ESD circuits tend to occupy usable chip area that could otherwise be used for implementing the main function of the chip. It would be desirable to provide ESD circuits on an area of the chip that cannot ordinarily be used to implement the main function of the chip, thereby making more chip area available for such function.
Moreover, as is now practiced, some portions of a chip are generally considered unusable for implementing the main function of the chip. Such portions include parts of the chip, over which the bond pads or other external terminals, e.g. lands or under bump metallization of the chip are located. Such parts are considered unusable because of high heat and pressure that are applied there during the packaging process. Other parts of the chip, as well, are traditionally considered unusable, such as parts along the edges of the chip near locations where they are diced.
It would therefore be desirable to provide ESD circuits in such locations, especially under bond pads, that are traditionally considered unusable areas of the chip, thus preserving more usable area for that which implements the main function of the chip.
In addition, ESD protection circuits generally operate by a principle of avalanche breakdown due to an excessively high voltage placed across a reverse-biased diode, referenced to ground. The reverse-biased diode is conductively connected between the external terminal of the chip and ground, in parallel with wiring to functional circuitry of the chip. Under normal conditions, when static charges are not present, the reverse-biased diode does not conduct, because the breakdown voltage of the diode has not been reached. On the other hand, when a high voltage is present at the external terminal, such as an electrostatic voltage, the reverse-biased diode undergoes avalanche breakdown, and current flows between the external terminal and ground.
One way of achieving device operation similar to a reverse-biased diode is with a field effect transistor (FET) having its gate tied to a particular potential below its threshold voltage. Under some conditions, when a voltage below threshold is applied to the gate of an FET, the FET behaves like a reverse-biased diode. Like a reverse-biased diode, under normal conditions, when the source to drain voltage (Vds) is not high, the FET does not conduct, because of the reverse-biased pn junction between the drain and the channel of the FET. However, when Vds becomes sufficiently high, avalanche breakdown occurs, and the FET then conducts.
It would therefore be desirable to provide ESD circuits in an area of a chip that is ordinarily considered unusable for circuitry which supports the main function of the chip, such as an area under a bond pad.
It would further be desirable to form an ESD circuit at the same time as other devices on the same chip, by at least some of the same steps in a process used to form the other devices of the clip.
It would further be desirable to provide a compact ESD circuit utilizing a plurality of compact transistors such as those used in a dynamic random access memory (DRAM).
It would further be desirable to provide a compact ESD circuit utilizing a plurality of vertical transistors of an array of transistors formed substantially according to steps of a DRAM fabrication process.